Beyond Exhaustive Simulation: Uncertainty-Aware Machine Learning for Power Delay Optimization in CMOS VLSI

The simultaneous power and delay minimization has become an important challenge in VLSI due to deep nanometre scaling of CMOS technology. Due to the non-linear and combinatorial interaction of supply voltage, threshold-voltage assignment, transistor sizing, body biasing, and buffer insertion, exhaustive design space exploration based on SPICE is infeasible. This paper proposes a framework of alternating optimization aided by a Machine Learning Algorithm in which most of the simulator calls are replaced with a surrogate of a learnt model. Graph neural networks based on transformer capture netlist long-range dependencies, and physics-informed networks embed analytical power-delay relationships. Multi-objective Bayesian optimization looks in the surrogate using expected hypervolume improvement, and calibrated uncertainty from deep kernel learning is supplied for importance-weighted active learning. The framework has shown a mean power reduction of 31.2% and a mean delay reduction of 21.4% yielding a 45.8% power-delay product improvement on eight digital benchmarks. The implementation takes 25 times less wall-clock time compared to simulation-driven search. The reported error in surrogate for power is 1.9% and 1.7% for delay. Optimization of CMOS VLSI circuits is uncertainty-aware and data-efficient..