IMPLEMENTATION OF OPTIMIZED RECONFIGURABLE BUILTIN SELF-REPAIR SCHEME FOR RAMS IN SOCS

Random Access Memory (RAM) is a critical component of modern System-on-Chip (SoC) designs, and its reliability directly affects overall chip performance and manufacturing yield. As VLSI technology advances, memory circuits become more susceptible to manufacturing defects and operational faults, making efficient testing and repair mechanisms essential. Conventional Built-In Self-Test (BIST) techniques can detect memory faults but may require additional hardware resources and may not provide an effective repair mechanism for different memory configurations. This project presents an optimized Reconfigurable Built-In Self-Repair (ReBISR) scheme for embedded RAMs in SoCs. The proposed approach integrates memory testing, fault detection, redundancy analysis, and repair configuration to improve memory reliability. A reconfigurable BuiltIn Redundancy Analysis (ReBIRA) circuit is designed to support different RAM sizes and redundancy organizations, while an adaptive fusing methodology aims to reduce repair setup time. The document also describes Cellular Automata Linear Feedback Shift Register (CA-LFSR)-based test pattern generation as an alternative to conventional LFSR-based testing, along with FPGA-based design verification using hardware description languages and simulation tools. The proposed approach aims to reduce hardware area overhead, improve fault detection and repair efficiency, and increase memory yield and reliability. It can be useful in embedded systems, automotive electronics, consumer devices, aerospace applications, and other SoC-based systems where dependable memory operation is essential. Overall, the project emphasizes the importance of reconfigurable memory testing and self-repair techniques in developing reliable and cost-effective VLSI systems.