SYNDROME BASE DECODING ALGORITHM FOR DOUBLE ERROR CORRECTION CODES

The project titled “Syndrome-Based Decoding Algorithm for Double Error Correction Codes” focuses on improving the reliability of memory systems by detecting and correcting errors in stored data as well as in the supporting encoder and decoder circuits. Traditional memory systems use Error-Correcting Codes (ECCs), such as Hamming codes, to correct single-bit errors and detect double-bit errors. However, these systems generally do not adequately address transient faults occurring within the encoder and decoder circuitry, which can lead to incorrect data processing and system failures. The proposed system employs a fault-tolerant memory architecture using syndrome-based error detection, fault-secure detectors, and error-correction techniques. The information vector is encoded into a codeword using a generator matrix and stored in memory. During data retrieval, a syndrome is calculated using the received codeword and the parity-check matrix to identify potential errors. The system uses a detect-and-repeat mechanism to verify encoder and corrector outputs, repeating operations when errors are detected. Periodic memory scrubbing is also performed to identify, correct, and rewrite erroneous data, preventing errors from accumulating beyond the correction capability of the code. The design also incorporates Euclidean Geometry Low-Density Parity-Check (EG-LDPC) codes and Projective Geometry codes to support fault-secure error detection and reliable data processing. The proposed architecture aims to improve data accuracy, reduce the probability of undetected errors, and increase the reliability of memory and communication systems. The design can be implemented and verified using hardware description languages such as Verilog or VHDL, with simulation tools such as ModelSim and Xilinx ISE. Overall, the project provides a fault-tolerant approach to double-error correction and protection against transient faults in memory storage and supporting logic circuits.