Project Angelica Revisited: A Rare-Earth-Oxide Lattice Bridge and Graded Compression Engineering for GaN-on-Si

GaN on large, cheap silicon wafers is the industry’s route to affordable power and RF electronics, but GaN and Si differ by 17 % in lattice constant and by a factor of two in thermal expansion. Project Angelica asks one question: can a rare-earth-oxide foundation between Si and the nitride make GaN-on-Si easier to build? The question is followed through a reproducible multi-physics model in which every constant carries a source. A (Gd₀.₅₈Eu₀.₄₂)₂O₃ base is lattice-matched to Si(111) at its 650 °C growth temperature. It was chosen with Angie’s Mixes, an open compound-selection framework. Two composition grades carry the stack upward. Grading-O, in the oxide, is a lattice bridge to a nitrided ScN cap. Grading-N, in the nitride (AlN→GaN), stores compression by threading-dislocation inclination and is jointly calibrated to measured wafers. Fracture, Schrödinger–Poisson transport, 2D thermal, charged 2D breakdown and RF-loss models follow the stack to the device. Differential Evolution, Monte Carlo, slip, dynamic-Ron, electro-thermal and cost models stress-test it. A running scoreboard records what the oxide wins, ties and costs. Main results: A 0.12 µm oxide moves a 650 V buffer inside the stress/bow window. Under shared model uncertainties, Angelica designs pass in 17–30 % of samples, against 9 % for the conventional stack. The 650 V buffer can be 17 % thinner if the oxide carries its DC voltage share. The cost is 3–10 % higher thermal resistance. Every claim is tagged IMPLEMENTABLE, TESTABLE or CONCEPT, and one command regenerates every number. This record contains the formal paper in English, Traditional Chinese and Japanese, a Primer in all three languages, and the full code and sources (manuscript CC BY 4.0, code Apache 2.0). The Reader’s Guide remains in version 1 (DOI 10.5281/zenodo.23806034). This revised edition (October 2026) replaces the first edition (June 2026, DOI 10.5281/zenodo.20608888). All changes are documented in the section “Relation to the first edition”. v2 update (October 2026). Version 2 pushes the applications further, with every new number reproducible from the code: Wafer size and voltage. On 300 mm wafers no conventional single-grade stack of the model fits the stress/bow window. Angelica fits with 0.46–1.35 µm of oxide, even if the oxide blocks only its capacitive share. At 1200 V a conventional stack also fits on 2 mm Si. Angelica moves the 1.5 mm Si case inside with 0.34 µm of oxide, or cuts the stack by 38 % if the oxide carries DC. An industry strain-relief stack already reaches 300 mm, so Angelica is presented as added margin, not as the only route. Monolithic power ICs. The oxide alone does not stop back-gating at switching speed. A source-tied ScN back-plane on the oxide could, for half-bridges up to about 150 V. Other applications. Bidirectional 800 V switches, RF loss converted to power-amplifier output (worst-case bounds), and a bonding rule for transfer to diamond (below about 150–175 °C). The update also covers size rules for released MEMS membranes and thermal-neutron capture in the (Gd,Eu) base: about 4 %, harmless, and a possible built-in detector. Memristors stay a concept. Process changes. Three new go/no-go experiments; the version-2 changes were checked by an independent review before release. Apart from these additions, the version-1 content is unchanged; see “Relation to the first edition”.