Fixed-Bias Stream Computing in Filamentary RRAM Crossbars: A Measurement-Calibrated Device–Circuit Study

Filamentary metal–oxide RRAM conducts through a tunneling gap for which the current grows exponentially with bias, so its Read-range I–V characteristic follows a sinh(V/V0) law. This introduces a systematic, input-dependent multiply–accumulate (MAC) error when used in analog Compute-in-Memory (CiM) accelerators with inputs encoded as voltage amplitudes. Because the nonlinearity also varies with resistance state, a single correction factor cannot generally compensate for all programmed weights. We present a measurement-calibrated device-to-circuit study of this error and show how it can be mitigated by replacing voltage-amplitude inputs with fixed-bias time-domain inputs, as in Asynchronous Stream Computing (ASC), which uses constant-amplitude sigma–delta streams. RRAM samples from two independent processes, Pt/Ti/HfO2/Ta/Pt and Al/TiO2/Au/Ti, are characterized, and the Stanford compact model is calibrated to each process. Together with two published parameter sets, the fitted nonlinearity coefficient V0 spans 0.29– 0.55V across four stacks and varies with resistance state within individual devices. In 65nm circuit simulations, voltage-amplitude encoding incurs up to 30% relative error in a single cell and approximately 8.5% full-scale-normalized error in single-bitline crossbars of 4 to 256 rows. At a 5ms accumulation window, ASC reduces the array error to 0.4–0.8% with ideal-integrator readout and 0.8–2.3% with transistor-level AΣΔM readout. Under measured device variability, group-balanced Monte Carlo simulations yield 7.6–9.2% analog error versus 0.5–0.7% ASC error. Wire resistance reduces the fixed-bias advantage but does not eliminate it within the simulated conditions. First-order energy estimates identify accumulation time and cell read current as important costs, while practical implementation also requires wordline drivers and high-ratio current division.