Wafer-Scale p-type TeSeO x for Complementary Oxide Electronics

Abstract The absence of a scalable p-type oxide semiconductor remains a major limitation for complementary oxide electronics, in part because improving hole conduction in amorphous oxide networks often coincides with increased defect-mediated leakage. Here, we report an anneal-free, wafer-scale predominantly amorphous tellurium selenium oxide (TeSeOx) p-type oxide semiconductor that achieves a more favorable balance between leakage suppression and hole conduction. Spectroscopic analysis and first-principles calculations indicate that Se incorporation reconfigures the local coordination environment, weakens the strongly Te–Te-dominated connectivity of Te-rich networks, and retains spatially connected valence-band states consistent with the experimentally observed partial recovery of on-state conduction. Consequently, p-channel field-effect transistors fabricated across 4-in. wafers exhibit a final screened yield of 91.4%, a mean mobility of 4.52 cm2 ·V–1 ·s–1, and wafer-scale uniformity without postdeposition annealing of the TeSeOx channel. Temperature-dependent transport measurements further support leakage suppression in the engineered network, with an on/off ratio exceeding 109 at 77 K. As a device-level proof-of-concept relevant to three-dimensional integration, vertically configured TeSeOx PFETs and IGZO NFETs were assembled into complementary inverters and multi-input logic gates, demonstrating correct functionality under a low thermal budget. Collectively, these results support local coordination engineering as a viable route toward scalable amorphous p-type oxide semiconductors for thermally compatible complementary oxide electronics, with potential relevance to 3D integration.