Electrical Modeling and Experimental Validation of Sub-5 μm GSG-TSV Interconnects Under Combined Electrothermal Coupling and Parasitic Surface Conduction for 3D ICs

Through-silicon via (TSV)-based 3D ICs continue to scale with advanced CMOS technology nodes. TSV interconnects therefore operate over a wide operating-temperature range, set jointly by the ambient temperature and by self-heating under rising power density. As a result, the temperature dependence of their electrical behavior can no longer be neglected. To address this, a temperature dependence equivalent circuit model for ground signal ground through silicon vias (GSG-TSVs) is proposed in this paper. The model simultaneously incorporates electrothermal coupling effects and the parasitic surface conduction (PSC) effect. The model is validated against HFSS simulations for three geometries (2.5/12.5, 3.5/25 and 5/50 μm) and against measurements of a fabricated 3.5/25 μm GSG-TSV from −40 °C to 100 °C and from DC to 50 GHz. Good agreement and scalability are achieved from −40 °C to 100 °C and from DC to 50 GHz. The influence of TSV size variations is further investigated. The results demonstrate that GSG-TSVs become increasingly susceptible to electrothermal effects as the diameter scales below 5 μm. This work provides a modeling methodology for analyzing the temperature-dependent behavior of TSV interconnects, including electrothermal coupling, over a wide temperature range.