From PLD-grown CuO optimization to CuO/SPB-02T hybrid thin-film transistors: structure–property–device correlations

Abstract Reliable p -type oxide thin-film transistors require simultaneous optimization of semiconductor growth and interface quality; however, these two aspects are commonly investigated independently. Although numerous studies have focused on optimizing CuO thin films or transistor performance independently, establishing a direct correlation between deposition conditions, material evolution, hybrid interface engineering, and statistically validated device performance remains an important challenge. Here, CuO thin films were deposited by pulsed laser deposition (PLD) under systematically varied substrate temperatures and oxygen pressures. Instead of directly fabricating TFTs after deposition, the optimum CuO semiconductor was first identified through comprehensive structural, morphological, and optical characterization using x-ray diffraction, scanning electron microscopy, UV–Vis spectroscopy, Tauc analysis, and Raman spectroscopy. The optimized CuO channel was subsequently integrated with an SPB-02 T overlayer to construct a hybrid TFT architecture. The resulting hybrid device exhibited a field-effect mobility of 0.194 ± 0.011 cm 2 V −1 s −1 , a threshold voltage of −0.17 ± 0.05 V, a subthreshold swing of 1.98 ± 0.15 V dec −1 , and an ON/OFF current ratio of (1.11 ± 0.11) × 10 5 , while also demonstrating excellent device-to-device reproducibility. The systematic comparison between the bare CuO and CuO/SPB-02 T transistors demonstrates that incorporation of the polymer overlayer is associated with substantial improvement in the electrical characteristics. The simultaneous improvement in field-effect mobility, threshold voltage, subthreshold swing, ON/OFF current ratio, hysteresis, and device-to-device reproducibility is consistent with modification of the electronic environment at the CuO back surface. However, the present measurements do not uniquely distinguish among possible contributions from surface-state modification, electrostatic charge redistribution, and contact-related effects. By integrating systematic semiconductor optimization with targeted hybrid interface modification, this work establishes a growth–structure–interface–device correlation for p -type CuO thin-film transistors.