Approximate computing circuits for error-tolerant applications with low energy consumption

Energy efficiency is a crucial factor in very large-scale integrated (VLSI) circuit design, and traditional methods offer limited solutions to power intensive circuits. Recently, approximate computing techniques have emerged, enhancing key design parameters like power consumption, propagation delay, and area, albeit with a compromise in accuracy. These techniques are especially suitable for high-performance computing, as they offer reduced energy consumption while compromising some accuracy, making them ideal for use in arithmetic circuits. This paper introduces enhanced versions of approximate adders (AxAs) and subtractors (AxSCs) for fundamental operations. Building upon these designs, approximate multipliers using the Wallace tree multiplier (AxWTM) and approximate dividers (AxDs) have been developed, and their performances have been compared regarding power consumed, spatial requirements, delay time, and error frequency. Many digital image and video processing applications, along with other multimedia tools, can function effectively even with slight inaccuracies in their output results. The existing and proposed designs were applied to image squaring, image multiplication, image subtraction, and image division applications, and peak signal-to-noise ratio (PSNR) was obtained. It is found that the suggested approximate designs achieved a better PSNR for all image applications, and the results were superior to those of their counterparts.