面对大模型高效能存算分离架构

Abstract The evolution of contemporary large language models (LLMs) remains constrained by an architectural bottleneck dominated by the brute-force scaling of compute and GPU memory. The mainstream Transformer architecture is limited by the O(N^2) complexity of its attention mechanism and therefore must keep the full key–value cache (KV cache) resident in extremely expensive high-bandwidth memory (HBM). Technology firms have attempted to compensate for software-level inefficiencies through the physical expansion of cloud-based intelligent computing clusters comprising tens of thousands of GPUs. This approach not only incurs substantial energy consumption—the so-called “VRAM wall” problem—but also leads to severe concurrency failures in centralized cloud inference and to increased market concentration. This paper proposes a system-level paradigm shift: rather than pursuing further compute scaling, it advocates deep topological optimization of memory and storage. The proposed architecture draws on the “chunk loading” and “spatial teleportation” logic of open-world game engines to achieve a complete decoupling of logical retrieval scheduling from deep logical inference. We propose and formally define five core mechanisms: an independent navigation memory layer, semantic closure anchors, Temporal Teleport Mapping (TP-Mapping), spawn-point persistent snapshots, and a native compliance and safety circuit-breaking layer. On this basis, we construct a fat-client/thin-server device–cloud collaborative concurrency-offloading model. Theoretical derivation and complexity analysis indicate that the proposed architecture reduces the time complexity of long-text retrieval to O(1) at the addressing stage and enables a single personal computer equipped with a consumer-grade GPU and 32 GB of commodity DRAM to achieve energy efficiency that, under the stated analytical assumptions, may exceed that of industrial-grade multi-GPU clusters. The architecture also eliminates high-concurrency downtime risk while providing strong data privacy protection and content-safety compliance. The present work is intended as a systems-level and analytical proposal; empirical validation is left to future work. Keywords: storage–compute disaggregation; VRAM wall; chunk loading; temporal addressing; state snapshot; edge computing; native compliance; low-cost AI

Authors

Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2026-10-30
DOI
https://doi.org/10.5281/zenodo.23788173
Primary Topic
Parallel Computing and Optimization Techniques
Type
preprint
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preprint

面对大模型高效能存算分离架构

笑然 潘
2 links
Zenodo (CERN European Organization for Nuclear Research)
Parallel Computing and Optimization Techniques
preprint

面对大模型高效能存算分离架构

笑然 潘
preprint en

Abstract

Abstract The evolution of contemporary large language models (LLMs) remains constrained by an architectural bottleneck dominated by the brute-force scaling of compute and GPU memory. The mainstream Transformer architecture is limited by the O(N^2) complexity of its attention mechanism and therefore must keep the full key–value cache (KV cache) resident in extremely expensive high-bandwidth memory (HBM). Technology firms have attempted to compensate for software-level inefficiencies through the physical expansion of cloud-based intelligent computing clusters comprising tens of thousands of GPUs. This approach not only incurs substantial energy consumption—the so-called “VRAM wall” problem—but also leads to severe concurrency failures in centralized cloud inference and to increased market concentration. This paper proposes a system-level paradigm shift: rather than pursuing further compute scaling, it advocates deep topological optimization of memory and storage. The proposed architecture draws on the “chunk loading” and “spatial teleportation” logic of open-world game engines to achieve a complete decoupling of logical retrieval scheduling from deep logical inference. We propose and formally define five core mechanisms: an independent navigation memory layer, semantic closure anchors, Temporal Teleport Mapping (TP-Mapping), spawn-point persistent snapshots, and a native compliance and safety circuit-breaking layer. On this basis, we construct a fat-client/thin-server device–cloud collaborative concurrency-offloading model. Theoretical derivation and complexity analysis indicate that the proposed architecture reduces the time complexity of long-text retrieval to O(1) at the addressing stage and enables a single personal computer equipped with a consumer-grade GPU and 32 GB of commodity DRAM to achieve energy efficiency that, under the stated analytical assumptions, may exceed that of industrial-grade multi-GPU clusters. The architecture also eliminates high-concurrency downtime risk while providing strong data privacy protection and content-safety compliance. The present work is intended as a systems-level and analytical proposal; empirical validation is left to future work. Keywords: storage–compute disaggregation; VRAM wall; chunk loading; temporal addressing; state snapshot; edge computing; native compliance; low-cost AI

Zenodo (CERN European Organization for Nuclear Research)
Parallel Computing and Optimization Techniques
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面对大模型高效能存算分离架构 — 笑然 潘 · Zenodo (CERN European Organization for Nuclear Research) (2026) | TGRS Research Map | TGRS