Effects of DBC Copper Layer Thickness on the Electrical, Thermal, and Thermo-Mechanical Performance of Parallel SiC Chip Power Modules

Direct Bonded Copper (DBC) substrates simultaneously provide current conduction, heat spreading, and structural support in multi-chip power modules, making Cu thickness a key trade-off variable. This study investigates the effects of DBC Cu thickness on the electrical, thermal, and thermo-mechanical responses of a 300 A parallel SiC chip power module. Thermal-coupling analysis was performed to distinguish the temperature effects of chip spacing from those of top Cu thickness. Electro-thermal simulation showed that conduction loss and maximum chip temperature increased as the top Cu thickness decreased, with a pronounced change between 0.175 and 0.160 mm under the 300 A condition. Thermo-mechanical analysis showed that reducing the symmetric top/bottom Cu thickness from 0.30/0.30 to 0.15/0.15 mm decreases reflow warpage of the baseplate from 183.930 to 30.091 μm. Thermal-cycling analysis showed that the cycle increment in volume-averaged inelastic strain energy density in the evaluated solder region decreased by 17.2%. The results showed distinct thickness-dependent responses: reducing the top Cu thickness increased conduction loss and maximum chip temperature, whereas symmetrically reducing both the top and bottom Cu thicknesses decreased reflow warpage and solder inelastic strain energy density in simulation.