Study of copper bottom-up filling method for through silicon via
This study investigated copper electroplating conditions for void-free filling of high-aspect-ratio through-silicon vias (TSVs). Seed-layer reinforcement using copper pyrophosphate plating improved seed coverage at the via bottom, promoting stable copper nucleation during subsequent sulphate copper electroplating and enhancing bottom-up filling behaviour. For TSVs with an aspect ratio of 5, filling behaviour was strongly influenced by the concentration balance of SPS and DAP in the presence of PEG. An appropriate SPS concentration promoted uniform bottom-up filling, whereas non-optimised additive compositions resulted in reduced bottom growth and pinch-off. For TSVs with an aspect ratio of 10, conventional plating conditions led to severe void formation because of restricted transport of electrolyte and additives within the vias. The application of jet-flow plating improved mass transport and additive supply, enabling successful void-free filling. These results demonstrate that seed-layer quality, additive balance, and hydrodynamic conditions are key factors governing copper filling behaviour in high-aspect-ratio TSVs.
Authors
- Katsuhiko TASHIRO (ORCID: https://orcid.org/0000-0003-2815-7280)
- Yoshio Horiuchi
- Hideo HONMA
- Yasushi UMEDA
- Sho Kitaguchi
Institutions
- Kanto Gakuin University (JP)
- YKK (Japan) (JP)
Publication Details
- Journal
- Transactions of the IMF
- Published
- 2026-10-29
- DOI
- https://doi.org/10.1080/00202967.2026.2748357
- Primary Topic
- 3D IC and TSV technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00