RAM-based coincidence window optimization for robust real-time muon reconstruction in the ATLAS Level-0 endcap muon trigger

The Large Hadron Collider (LHC) at CERN provides the world’s highest center-of-mass energy proton–proton collisions. The ATLAS detector, located at one of the collision points, aims to perform precision measurements of Standard Model processes and to search for phenomena beyond it by observing particles produced in these collisions. From 2030, the High-Luminosity LHC (HL-LHC) will begin operation, increasing the instantaneous luminosity by about a factor of three. In preparation for HL-LHC, we report on studies of firmware optimization for the first-level muon trigger in the HL-LHC ATLAS experiment. Real-time muon track detection is implemented around a “Coincidence Window”, which projects hit combinations across three detector stations into momentum space through a predefined mapping. This is realized with RAM resources of FPGAs, where the input addresses correspond to hit patterns and the output to the associated track parameters. In the endcap region, the reconstruction principle is based on the point-angle measurement, and the reconstructed tracks are expected to follow straight-line trajectories. Non-straight combinations are rejected with null outputs, thereby serving as a pattern finding mechanism. Optimization is performed, respecting different tasks for the three stations: while the first and third stations mainly determine the momentum, the second station serves as a confirmation layer. Relaxing the straight-line constraint in the second station within a controlled range improves efficiency in the presence of multiple scattering and maintains robust performance against detector misalignments. As a result, the plateau efficiency for transverse momentum improves from 93.7% to 94.5% in the nominal configuration, and from 85.9% to 93.5% under a misalignment model based on Run-1 alignment constants. This optimization achieves a significant performance gain without increasing FPGA resource usage or latency. Moreover, it contributes to overall resource reduction and design simplification of the trigger system.