Uniformity Enhancement in 3D NAND Etch Processes via N₂ Bubbling Si₃N₄ Removal and Poly-Si Etch-Back

The push for increasingly large-capacity non-volatile data storage necessitates an improvement in NAND flash memory technology. It challenges high volume manufacturing (HVM) to incorporate more complicated three-dimensional structures, such as gate line and channel hole architectures, that have ever-increasing aspect ratios. Consequently, in advanced NAND flash memory manufacturing, the etch back of the polysilicon (poly-Si) film in channel holes and the selective removal of Si 3 N 4 /SiO 2 film stacks in the gate line, are two crucial processes that help determine device performance. However, as the specifications of wet etch processes evolve, these two key process steps suffer issues of poor etch uniformity and serious by-product regrowth. Herein, we present an advanced N 2 bubbling technology incorporated in an ACM Ultra C wet bench (WB) tool, that addresses these concerns. The performance of the poly-Si etch back and selective silicon nitride (SiN) removal steps on blanket film wafers (BW) both showed significant improvements, which were ultimately demonstrated on patterned wafer (PW). Keywords: NAND flash memory manufacturing, gate line, channel hole, N 2 bubbling technique, etch uniformity, byproduct regrowth