Novel Projected-Pitch Technology and Non-Planar Surface LDMOS with Ultra-Low Specific On-Resistance

Abstract This paper proposes a Non-Planar Surface LDMOS (NPS-LDMOS) structure based on a projected-pitch technology to decrease the specific on-resistance (RON,SP). By rotating a portion of the drift region, NPS-LDMOS creates a source-drain height difference, which shortens the projected distance of the cell-pitch along the horizontal axis and optimizes current flow paths. Based on a well-calibrated 55 nm BCD platform, the NPS-based LDMOS devices are developed for the 8 V, 9 V, 10 V and 16 V voltage levels with comparable off-state breakdown voltage (BVOFF), all achieving an improvement of over 25% in the static figure of merit (sFOM=BVOFF 2 /RON,SP) and over 30% in the dynamic FOM (dFOM=RON,SP×QG). Targeted parameter optimization is performed for the 16 V NPS-LDMOS, yielding a BVOFF of 27.9 V and a reduced RON,SP of 2.851 mΩ•mm², representing a 68.3% improvement in sFOM (27.3 MW/cm²) over conventional LDMOS. In terms of dynamic performance, the customized 16 V device exhibits lower output capacitance and reduced gate charging time. The projected-pitch technology constitutes a novel approach to sustain Moore's Law and exhibits significant potential to drive the development of next-generation BCD platform.