Future Challenges in Semiconductor Cleaning

Wet etching had received more attention than pre-and post-cleaning from 1950s to 1970s. However, in the era after the 5um node, wet etching was replaced by dry etching due to its isotropic etching characteristics. Therefore, pre-and post-cleaning are considered a major part of cleaning except for several wet etching processes. However, in the current era of 3D structured devices such as VNAND, GAA, 3DDRAM, lateral wet etching is essential for the patterning of 3D devices, the proportion of wet etching in cleaning processes is increasing. Additionally, selective partial uniform recess technology is sometimes required instead of selective full strip, so local, top-bottom and in-wafer uniformity have become more important than ever. To achieve those requirements, longer time process and in wafer uniformity control hardware, such as nozzle sweep and heating chuck have been used. From time to time, we must control the selectivity between the same materials with different concentration, such as Si x Ge 1- x , to obtain the target shape; we must use more flexible, multi-step processes. Dry (gas phase) cleaning provides better flexibility than wet cleaning. Furthermore, dry (gas phase) cleaning gives us another chance for several materials that are not compatible with wet chemical cleaning, providing another domain of selectivity. Also, area selectivity become another challenge. We must etch without corner rounding or climbing, and we want to perform anisotropic etching. On the contrary, based on generic clean roadmap, high aspect ratio cleaning, and low consumption cleaning will be continuous challenges. Countermeasures for both challenges are also briefly discussed.