Ultra‐Efficient Memristive Voltage‐Resistance Logic Framework With Integrated Readout Strategy Based on Hafnium Zirconium Oxide

ABSTRACT The integration of logic operations and data storage is regarded as a promising strategy for enabling edge computing, a key requirement for real‐time, data‐intensive scientific and industrial applications. Achieving edge‐capable computing, however, requires exceptional spatiotemporal efficiency, and many previously proposed logic schemes still face substantial limitations. Here, we introduce a memristive voltage–resistance (V–R) logic strategy that infers output resistance states without additional incurring area or latency penalties. The approach relies on integrated readout of the discharge behavior into programming of a two‐terminal capacitor‐type memristor. Implemented in an HfO 2 ‐based ferroelectric tunnel junction (FTJ) device with multiple resistive states, this strategy enables a half adder to be computed using a single device in a single step, and a 1‐bit full adder using only three FTJs in three steps—achieving previously unattainable spatiotemporal cost for execution of standard benchmarking tasks. Our work provides a pathway to edge computing by maximizing the spatiotemporal efficiency achievable with memristor‐based logic‐in‐memory.