Experimental Analysis of Electro-Thermal Gradient Effects in Monolithic LDO Regulators

This paper experimentally investigates the impact of on-chip thermal gradients on the accuracy of a monolithic low-dropout regulator (LDO). Measurements from a silicon prototype show that load-induced temperature gradients introduce systematic, load-dependent reference voltage errors that are not captured by conventional electrical simulations. An analytical electro-thermal model is used to interpret the measured behavior and to identify the dominant physical mechanisms responsible for the observed drift. Experimental results demonstrate that suboptimal layout can lead to reference voltage deviations exceeding 60 mV under full-load conditions, highlighting the limitations of conventional symmetry in mitigating thermal effects. However, by employing the proposed thermally aware floor-planning, this error is successfully reduced to just −6 mV, achieving a one-order-of-magnitude accuracy improvement without altering the electrical schematic. The presented analysis provides design-relevant insights into device placement, biasing, and power stage integration for monolithic power management ICs.