Architecture for Managing a 2^7-Node Network Using a Threshold-Based Combinational Circuit Designed Specifically to Bypass Routing Conflicts and Prevent Systemic Deadlocks

Physically constructing geometric figures is bound to three spatial dimensions; structures existing in four or more dimensions can typically only be conceptualized or simulated virtually. This work presents the spatial realization of a 7-dimensional (7D) network topology mapped into a 3-dimensional (3D) physical space. The network consists of 2^7 = 128 nodes, where each node is uniquely identified by a 7-bit binary address. To ensure a collision-free and deadlock-free environment, the 128 nodes are arranged in a deterministic geometric pattern. Routing paths within this network are predefined using a deterministic algorithm. The exact packet travel paths between any given source and destination node are computed using sequential Exclusive-OR (XOR) operations applied to their binary addresses. Rather than relying on classical CMOS-based logic, this routing architecture utilizes a novel XOR gate model built upon Multiple-Input Threshold Logic (MITL). While this MITL framework is versatile enough to synthesize fundamental logic primitives (AND, OR, NOT) and complex sequential circuits, this specific implementation leverages a specialized arrangement of 56 MITL-based XOR gates. This circuit configuration successfully computes deadlock-free routing paths dynamically, ensuring that data packets transit through a bounded path consisting of at most 8 nodes. Based on the experimental input?output values, the network's truth tables demonstrate robust topological constraints. When applying the routing algorithm, the maximum path length is strictly confined to 7. Specifically, evaluating any source?destination pair generates a path sequence of exactly 8 node positions (inclusive of the source and destination). Because certain nodes within this sequence may share identical values, the number of unique nodes involved in any given path is at most 8, ensuring the actual path length remains less than 8. Furthermore, the implemented network design is verified to be entirely collision-free. This is structurally validated by the truth tables, which exhibit no duplicate node identifiers within any single column.

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Publication Details

Journal
International Journal of Science and Research (IJSR)
Published
2026-10-28
DOI
https://doi.org/10.21275/sr261023143302
Primary Topic
Interconnection Networks and Systems
Type
article
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article

Architecture for Managing a 2^7-Node Network Using a Threshold-Based Combinational Circuit Designed Specifically to Bypass Routing Conflicts and Prevent Systemic Deadlocks

Anup Kumar Biswas
International Journal of Science and Research (IJSR)
Interconnection Networks and Systems
article

Architecture for Managing a 2^7-Node Network Using a Threshold-Based Combinational Circuit Designed Specifically to Bypass Routing Conflicts and Prevent Systemic Deadlocks

Anup Kumar Biswas
article en

Abstract

Physically constructing geometric figures is bound to three spatial dimensions; structures existing in four or more dimensions can typically only be conceptualized or simulated virtually. This work presents the spatial realization of a 7-dimensional (7D) network topology mapped into a 3-dimensional (3D) physical space. The network consists of 2^7 = 128 nodes, where each node is uniquely identified by a 7-bit binary address. To ensure a collision-free and deadlock-free environment, the 128 nodes are arranged in a deterministic geometric pattern. Routing paths within this network are predefined using a deterministic algorithm. The exact packet travel paths between any given source and destination node are computed using sequential Exclusive-OR (XOR) operations applied to their binary addresses. Rather than relying on classical CMOS-based logic, this routing architecture utilizes a novel XOR gate model built upon Multiple-Input Threshold Logic (MITL). While this MITL framework is versatile enough to synthesize fundamental logic primitives (AND, OR, NOT) and complex sequential circuits, this specific implementation leverages a specialized arrangement of 56 MITL-based XOR gates. This circuit configuration successfully computes deadlock-free routing paths dynamically, ensuring that data packets transit through a bounded path consisting of at most 8 nodes. Based on the experimental input?output values, the network's truth tables demonstrate robust topological constraints. When applying the routing algorithm, the maximum path length is strictly confined to 7. Specifically, evaluating any source?destination pair generates a path sequence of exactly 8 node positions (inclusive of the source and destination). Because certain nodes within this sequence may share identical values, the number of unique nodes involved in any given path is at most 8, ensuring the actual path length remains less than 8. Furthermore, the implemented network design is verified to be entirely collision-free. This is structurally validated by the truth tables, which exhibit no duplicate node identifiers within any single column.

International Journal of Science and Research (IJSR)
Industry, innovation and infrastructure
Openalex Percentile: Top 12%
Interconnection Networks and Systems
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Architecture for Managing a 2^7-Node Network Using a Threshold-Based Combinational Circuit Designed Specifically to Bypass Routing Conflicts and Prevent Systemic Deadlocks — Anup Kumar Biswas · International Journal of Science and Research (IJSR) (2026) | TGRS Research Map | TGRS