A Discrete‐Time Δ‐ΔΣ Direct‐Digitization AFE With 96.1‐dB SNDR and 4‐kHz Bandwidth for Electroencephalography (EEG) Acquisition

ABSTRACT To address the challenges posed by DC electrode offset, motion artifacts, and high electrode‐skin contact impedance to the input range and conversion accuracy of analog front ends (AFEs) for electroencephalography (EEG) acquisition, this paper presents a third‐order discrete‐time Δ‐ΔΣ direct‐digitization AFE. The proposed architecture employs a noninverting pseudo‐differential instrumentation amplifier, switched‐capacitor integrators, a 4‐bit successive‐approximation‐register (SAR) quantizer, and a digital accumulator (ACC). By subtracting the differential input voltages at two adjacent sampling instants, first‐order shaping of the input signal is achieved, thereby reducing the dynamic‐range (DR) requirement imposed by DC offsets and low‐frequency interference. Data‐weighted averaging (DWA) is employed to suppress unit‐mismatch errors in the multibit feedback DAC. The circuit is designed and laid out in a 180‐nm CMOS process and verified through post‐simulation. It operates at a sampling frequency of 1 MHz with a 1.8 V supply and consumes 1.07 mW. Post‐simulation results show that, with an 800‐mVpp differential input, the AFE achieves an SNDR of 96.13 dB and an SNR of 97.42 dB, and an input‐referred noise of approximately 3.8 μVrms over a 4‐kHz bandwidth. The SNDR‐based figure of merit FoM SNDR is 161.9 dB, and the system achieves a DR of approximately 100.73 dB. The input impedance is 3.367 GΩ at 100 Hz and remains 84.57 MΩ at 4 kHz. The proposed AFE achieves high conversion accuracy, a wide input range, and high input impedance, making it suitable for electroencephalography (EEG) acquisition.