Hardware-Tripped Phase Imbalance and Neutral Fault Detection System for Low-Voltage Distribution Grids

In Bangladesh’s low-voltage distribution network, power lines often get severely unbalanced. This happens because of heavy single-phase commercial loads, unequal consumer allocation across phases (A, B, C), and widespread illegal tapping. When one phase carries significantly more load than the others, a heavy return current flows through the neutral wire (IN ). This causes neutral line overheating, voltage fluctuations that damage home electronics, and frequent transformer coil burnouts. Traditional digital protection relays use a single microcontroller to run sampling loops (ADCs) and execute trip logic in software. But running code takes time—introducing 15 ms to 50 ms of processing delay. During a massive current surge, that delay is long enough to destroy transformer coils or freeze the processor entirely.This project solves the problem by splitting the job into two independent layers:• Layer 1 (DLD Hardware Protection): Pure logic gate ICs and comparators continuously monitor currents and cut off power in under 2 ms during a fault.• Layer 2 (ESP32 Edge Telemetry): The ESP32 handles secondary tasks—calculating imbalance percentages (PUF%), logging fault timestamps, and sending real time updates to a web dashboard