Coordinated Threshold-Voltage Reduction for a Sub-1 V 32-nm Bulk-FinFET mm-Wave Front-End: A TC-Cascode LNA, Current-Reuse Gilbert Mixer and Neutralized PA in PTM-MG

The contribution of this paper is a single, coordinated threshold-voltage reduction method for sub-1 V bulk-FinFET mm-Wave front-ends, in which three levers fin-count sizing, a shared substrate-tie body-bias bus, and transformer-coupled under-neutralization are applied to the low-noise amplifier, the down-conversion mixer and the power amplifier as one design rather than being optimised block by block. The novelty is the method and its circuit-level realisation; it is not the individual topologies, and not the simulator flow. Section 5 states precisely what changes inside each block relative to its conventional counterpart. The method is demonstrated on a 32-nm bulk-style FinFET (PTM-MG v2.1) front-end for 5G NR FR2 (28 GHz) and automotive radar (7677 GHz). A single body-bias bus at VBB = +0.15 to +0.25 V (γb = 30 mV/V) relieves headroom in all three blocks at once; the transformer-coupled cascode removes the stacked-device headroom penalty; and CN = 0.95 Cgd under-neutralization stabilises the gain without pushing the stage towards oscillation near fmax/3. Under a 0.9-1.0 V supply, the three-stage TC-cascode LNA delivers 23.9-25.6 dB gain with NFmin = 5.3 dB and a physically valid U-shaped noise profile across 70-82 GHz, giving FoMLNA = 23.0 dB at 77 GHz. The current-reuse Gilbert mixer reaches CG = 13.2 dB and DSB NF = 7.2 dB at 28 GHz on 5.4 mW. The neutralized TC-cascode PA reaches Psat = 14.6 dBm with 26.8% PAE at 28 GHz. All figures are proof-of-concept estimates from a predictive academic model; the limitations of that model, and the measurements needed to close them, are set out once in Section 8.