An electrical characterization framework for variability and manufacturability assessment in screen-printed interconnects

Abstract The manufacturability of printed electronics is often limited by process variability that affects electrical performance, manufacturing yield, and process consistency. Although electrical characteristics such as resistivity and sheet resistance are commonly reported, a standardized electrical framework for quantifying variability and manufacturing robustness remains lacking. This work presents a test-pattern-based framework for evaluating the electrical performance, variability, and yield of printed electronic interconnects. The framework combines geometry-dependent resistance and capacitance characterization with normalized scaling analysis, coefficient-of-variation measurements, open-circuit failure assessment, and functional yield evaluation. Using screen-printed silver conductors on polyimide substrates, the influence of conductor length, width, effective overlap length, print orientation, and impression number on electrical behavior is investigated. Resistance measurements demonstrate that conductor length follows expected geometric scaling more closely than conductor width. Variability and yield analyses identify conductor width as the dominant geometry-dependent limitation, with narrow-width structures exhibiting increased resistance variation, reduced functional yield, and a greater incidence of open-circuit failures. Impression-to-impression characterization further reveals measurable process drift during extended print runs. The proposed framework provides a practical methodology for quantifying manufacturing robustness, monitoring process consistency, and establishing geometry-dependent design guidelines for printed electronics technologies.