A Review of Machine Learning Techniques for Analog-To-Digital Converter Design Automation

ADCs play an important role in converting information from the analog world to the digital one; with modern applications requiring higher resolutions, speed, and power efficiency, it has become very difficult to design them. Traditionally, the design of an ADC follows an iterative design process that includes stages like specification, behavioral modeling, transistor sizing, schematic simulation, layout, and post-layout verification, which is laborious and requires much designer expertise due to the consideration of process-voltage-temperature variations and yield. In this work, we perform a review of the latest advancements in the use of machine learning (ML) to tackle the challenges of ADC design in recent years, with systematic search from 2015 to 2026 in IEEE Xplore, ACM Digital Library, and arXiv. Rather than organizing the literature on different ML algorithms, this paper categorizes ML approaches such as regression, tree-based models, SVM, ANN, CNN, GNN, reinforcement learning, evolutionary algorithms, and Bayesian optimization in ADC design stages such as behavioral modeling, transistor sizing, calibration of comparators and capacitor arrays, calibration of ADC, layout optimization, prediction of PVT/yield variations, and design space exploration. Comparative analysis includes the benefits provided by each technique such as speed and accuracy improvements, as well as their main drawbacks. Open challenges are then presented, including lack of data, poor generalization performance, low explainability, and the largely unexplored topic of co-optimization across multiple stages. Finally, future trends in the field are presented in terms of new directions such as generative AI, GNN-based layout optimization, physics-informed learning, digital twins, and human-AI collaborative design, as well as risks and potential problems such as manufacturability and IP in generative approaches