AETHER-ISA: Hardware Architecture Specification & Dual-Track Open Hardware Framework (v1.0)

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Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2026-10-28
DOI
https://doi.org/10.5281/zenodo.23718016
Primary Topic
Embedded Systems Design Techniques
Type
article
Field-Weighted Citation Impact
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article

AETHER-ISA: Hardware Architecture Specification & Dual-Track Open Hardware Framework (v1.0)

Liew Hsiao Ling
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Zenodo (CERN European Organization for Nuclear Research)
Embedded Systems Design Techniques
article

AETHER-ISA: Hardware Architecture Specification & Dual-Track Open Hardware Framework (v1.0)

Liew Hsiao Ling
article en

Abstract

No abstract available for this paper.
Zenodo (CERN European Organization for Nuclear Research)
Openalex Percentile: Top 10%
Embedded Systems Design Techniques
DOIOpen Access PDFOpenAlex
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AETHER-ISA: Hardware Architecture Specification & Dual-Track Open Hardware Framework (v1.0) — Liew Hsiao Ling · Zenodo (CERN European Organization for Nuclear Research) (2026) | TGRS Research Map | TGRS