Digital Voting Machine Using Verilog

The Digital Voting Machine Using Verilog HDL is a digital system designed to count votes for four candidates automatically. It uses candidate inputs, clock and reset signals, edge-detection logic, and individual vote counters. A Verilog testbench is used to verify vote counting and analyze simulation waveforms using tools such as EDA Playground or Xilinx Vivado. This project helps students understand digital logic design, sequential circuits, counters, and simulation-based verification without requiring physical hardware. It is intended for educational purposes and can be extended with FPGA implementation and additional security features.