Application of asynchronous data bypass to increase performance of in-order superscalar RISC-V processor core

RISC-V is an open-source architecture that does not require license fees from pro-cessor core vendors. This allowed RISC-V to become widely distributed first in the micro-controller-class processor core market and subsequently in the market of higher-performance devices. Currently RISC-V processor cores with in-order execution, which combine mid-range performance, compactness, and energy efficiency are attracting the most interest from customers. This makes the task of continuing to improve them a highly relevant. This paper explores the application of a microarchitectural modification, asynchronous data bypass, to increase the performance of in-order superscalar RISC-V processor core. Asynchronous data bypass has been made for two pairs of functional blocks: between arithmetic-logic unit (ALU) and ALU, between ALU and branch unit. The main obstacle of implementing asynchronous data bypass is the creation of an extremely long logical path, which leads to violations of timing constraints. To overcome this obstacle, an approach was proposed that involves completely excluding a subset of instructions from asynchronous bypass and separating the logic of the remaining instructions into groups based on the length of the logical path. This approach made it possible to keep the logical path of asynchronous bypass no longer than the longest path of a single execution unit. The results showed that the use of asynchronous bypass can significantly increase the performance of in-order superscalar processor core. At the same time, the area overhead is very low.