Detection of Single Stuck-at and Bridging Faults in Cluster-based FPGA Architectures

This paper presents a new technique for detecting single stuck-at and bridging faults in cluster-based FPGA architectures, using same set of test vectors generated by a test pattern generator circuitry. This technique is based on configuration of logic elements using test logic structure and the outputs of two separated logic elements are compared to detect a fault. To do this, block under test, TPG and output response analysis circuitry are generated in FPGAs. The configurations of test pattern generation, block under test and output response analysis are also discussed in this paper. The novelty lies in the fact that the same set of test vectors can detect all the stuck-at as well as bridging faults if the test vectors are applied in a particular sequence and analyzing the output results. We presented a detail analysis of results to detect faults as well.