Architectural exploration and FPGA validation of a RISC-V instruction-set extension for Classic McEliece

Abstract NIST did not select Classic McEliece for standardisation in 2025 because it was sceptical that the scheme would see widespread use; the report nevertheless remained confident in its security, subject to a parameter-set qualification. In June 2026, Clause 13 of Amendment 2 to ISO/IEC 18033–2 specified the Classic McEliece KEM. This paper examines a tightly coupled RISC-V instruction-set extension (ISE) within an integrated implementation. Starting from the Kennedy–Halak RV32I ISE, we explore support-list Chien search, fixed-size Gaussian elimination for minimal-polynomial generation, and streaming systematic-form reduction for public-key generation. A direct-memory-access (DMA)-assisted candidate was rejected after integrated profiling showed only 1.0–1.1 $$\times$$ improvement in . We make the inherited design FPGA-executable by correcting its decryption path, moving the instructions into the RISC-V space, and replacing asynchronous memories with block-RAM-compatible synchronous memories. At $$\texttt{SYS}\_\texttt{T}=2$$ , $$\texttt{SYS}\_\texttt{N}=48$$ , and $$\texttt{GFBITS}=12$$ , the complete profile occupies 10,531 adaptive logic modules and reaches 118.89 MHz on a Cyclone V FPGA. Against an unaccelerated baseline under matched asynchronous-memory simulation, encapsulation cycle count is reduced by 87.4% and decapsulation by 86.1% (7.18 $$\times$$ ). The synchronous FPGA build completes both operations with host-generated keys and requires 3,654,113 decapsulation cycles. One reference known-answer test and four directed error-pattern tests pass. The key-generation accelerators are verified separately and in simulation, but software pushes full key generation beyond the 300-million-cycle budget. The evidence covers architectural analysis and reduced-parameter FPGA implementation; production-parameter performance and side-channel resistance remain unevaluated.