Negative-Capacitance Germanium-on-AlAs Nanosheet FETs for Ultra-Low-Power Logic Applications

Abstract This work presents the design and circuit-level evaluation of a lattice-matched germanium (Ge)-on-AlAs nanosheet field-effect transistor (NSFET) architecture incorporating a negative-capacitance (NC) gate stack for ultra-low-power logic applications. A calibrated Ge NSFET baseline was first established, followed by systematic optimization of nanosheet geometry, aspect ratio (scaled from 1 to 1/3), and sheet count (from 1 to 3) to maximize the I ON /I OFF ratio to 8.6 × 10 4 at a supply voltage of V DD = 0.5 V. Integration of a ferroelectric Hf 0.67 Zr 0.33 O 2 layer into the gate stack enabled marginal subthreshold slope reduction but increased I ON /I OFF to 1.1 × 10 5 for the n-NSFET at an aspect ratio of 1/3, while improving electrostatic control and maintaining a threshold voltage of 0.25 V, as well as a drain-induced barrier lowering (DIBL) of 40.5 mV/V and 43.0 mV/V, between the p-type and n-type devices, respectively, through dual work function engineering. The resulting NC-NSFETs were used to construct a complementary CMOS inverter, which demonstrated full rail-to-rail output swing, a sharp voltage transfer characteristic, and a logic threshold of ∼0.27 V. Transient simulations revealed a significant improvement in switching speed from 40 fs to 19 fs, particularly in the pull-down transition, confirming that the NC effect provides measurable benefits at both the device and circuit levels. These results establish the Ge NC-NSFET platform as a promising candidate for future ultra-low-power logic technologies.