Low-Power High-Speed Sense-Amplifier- Based Flipflops with Conditional Bridging Using Tanner Eda.

One of the major challenges in modern VLSI design is power consumption, right up there with space and performance. Digital systems rely on the flip-flop. In sub-threshold operation, we examine and contrast four different flip-flop topologies: IP-DCO, MHLFF, CPSFF, and CPFF. Both pulse-triggered and conditional approaches are included in these topologies. Very low power consumption applications are now within reach, thanks to sub threshold technology. One advantage of this technique is that it decreases the number of power-hungry flip-flops. Compared to a strong inversion circuit, a subthreshold circuit consumes less power while running at the same frequency. Tanner uses 18nm technology in cmos for design. We test the flip-flops' power delay, power delay product, and average power at a 1V power supply voltage and look at them from every perspective. Keywords: Sub Threshold Technology, Flip Flop, Low Power.