Root-Cause Analysis of ISA-Level Power Side-Channel Leaks in RISC-V Cryptographic Implementations

Masking is the standard defense against side-channel analysis (SCA) in cryptographic software, where sensitive variables are split into independent shares. While leaks in masked implementations are often attributed to microarchitectural effects, interactions at the instruction-set architecture (ISA) level can also introduce subtle vulnerabilities that compromise security in practice. To precisely characterize how ISA-level data interactions in full implementations lead to leakage, a systematic and efficient implementation-wide analysis is required. To this end, we introduce ISALeak, a target-agnostic framework for analyzing full masked implementations to identify and attribute the root causes of side-channel leakage at the ISA level. Specifically, ISALeak considers leakage associated with architectural register values and transitions between successive register states, providing an ISA-level abstraction of register-level data interactions. ISALeak supports both high-level implementations and hand-written assembly code, enabling precise side-channel leakage attribution regardless of the implementation level. Beyond detection, ISALeak localizes and explains leakage sources, complementing statistical methods such as TVLA. We evaluate ISALeak on masked AES and masked Ascon across multiple compiler versions and optimization levels. Using power measurements from ASIC (PicoRV32) and FPGA (Ibex) RISC-V cores, we show that 20–40% of the leaks detected by TVLA in masked AES are associated with register-level interactions identified by ISALeak. For masked Ascon, 17–23% of the observed leakage stems from ISA-level effects and is consistently reflected in physical power traces.