Cinco de MAYO: Accelerating Post-Quantum Multivariate Quadratic Signatures with RISC-V

MAYO is a digital signature scheme based on the multivariate public key cryptography paradigm, designed to provide security in the post-quantum setting. MAYO emerged as a promising candidate during the NIST Post-Quantum Cryptography (PQC) standardization process for additional digital signatures. In this work, we present the first RISC-V-based hardware-software co-design of MAYO. We accelerate the computational bottlenecks of AES-128-CTR-based seed expansion and GF(16) matrix multiplication by integrating a custom function unit (CFU) with a general-purpose RISC-V micro-processor. Our design is based on the open-source Vex RISC-V core implemented on an Artix-7 FPGA. Experimental results demonstrate performance speedups of 11-13x for Key Generation, 6-8x for Signing and 5-6x for Verification compared to the software-only baseline on the same RISC-V core, across different MAYO parameter sets. Additionally, our implementation incurs only 3-7% overhead in hardware resource consumption relative to the processor, thus resulting in significant improvement in area-time product. Our RISC-V-based hardware-software co-design achieves significant speedup compared to state-of-the-art assembly-optimized software on ARM Cortex-M4. In comparison with custom hardware accelerators, we achieve significant reduction in hardware resource utilization while supporting all MAYO parameter sets on a low-cost FPGA. Our results demonstrate that the proposed hardware-software co-design provides an efficient and practical solution for accelerating MAYO in resource-constrained embedded platforms.