A novel approximate multiplier architecture for optimizing power and precision in image-centric applications

Approximate multiplication suits image filters when the arithmetic error stays within the image-quality tolerance of the output. This paper presents a 16-bit selective approximate multiplier whose adder is partitioned at bit 8. In each of the lower eight-bit positions, an equality-controlled multiplexer selects either a newly generated sum or the preceding sum; the upper eight positions use an exact Brent–Kung prefix adder. The two middle-weight cross-terms of the product are omitted. The proposed multiplier and four reference architectures were implemented in Verilog, synthesized in Vivado 2026.1 for a Zynq-7020 field-programmable gate array and modelled in MATLAB for 3 × 3 Gaussian filtering of the Cameraman image. The proposed design uses 183 look-up tables and has a 2.959 ns critical path. It achieves a peak signal-to-noise ratio of 17.97 dB, compared with 7.69–8.13 dB for the reference designs, showing that the placement of approximation strongly affects the accumulated filtering error.