Effect of the Channel Hole Diameter with Device Variation on 3D NAND Flash Memory

This work investigates the impact of channel hole geometry and fabrication-induced device variations on 3D NAND flash memory using three-dimensional technology computer-aided design (TCAD) simulations. The channel hole diameter (dhole) is varied over a practical range, tapered and elliptic profiles are introduced to emulate high-aspect-ratio etch distortion, and oxide-nitride-oxide (ONO) thickness fluctuation is applied to reflect deposition non-idealities. The study focuses on the programmed threshold voltage (Vth), subthreshold swing (SS), and bit-line (BL) current (IBL) of each WL and also includes the effect of read temperature in the typical operating range. The results indicate that reducing dhole increases the program efficiency while decreasing IBL. Regarding process variations, both increased ellipticity and ONO thickness were found to degrade the programmed Vth. However, while IBL increases notably with ellipticity, it exhibits a relatively weak dependence on ONO thickness. Furthermore, elevated read temperatures consistently reduce the apparent Vth and IBL, thereby tightening the sensing margin for multi-level operation. These findings elucidate the distinct impacts of geometric scaling on device variability and provide useful design guidelines for high-density memory architectures.