Design and Implementation of 3D FeNAND Array Interface Circuit for Compute-in-Memory Applications

Compute-in-Memory (CIM) has emerged as a promising solution for high-speed and energy-efficient artificial intelligence computation. Among various memory technologies, FeFET devices provide several advantages such as multi-level operation, high-density integration, and CMOS compatibility for CIM applications. This study presents a scalable 3D FeNAND array interface circuit for CIM systems, integrating high-voltage (HV) driver, source-line (SL) driver, and word-line (WL) MUX, that supports both high-voltage driving of memory devices for a wide memory window and reliable interfacing with low-voltage CMOS circuits. The HV driver, SL driver, and WL MUX are designed to have wide-range high-voltage generation with digital controllability, ultra-low memory current sensing(< 100 nA), and fast WL voltage switching (< 100 ns), respectively. The proposed chip was fabricated in a 180 nm BCD process and experimentally verified to support the target 8×3 3D FeNAND array by generating standby, erase, program, and read signals for CIM operation.