Performance Analysis on Silicon Bridge with Chessboard Patterned Interconnect

A signal integrity and routing density analysis of a chessboard patterned interconnect (CPI) structure for Si bridge-based die-to-die interconnects is presented, targeting compliance with the Universal Chiplet Interconnect express (UCIe) standard. The CPI structure is compared against conventional fully shielded (FS) S1G1 and SnG1 configurations through full-wave electromagnetic and time-domain simulations. Key electrical transmission performance metrics include S-parameters, power-sum crosstalk (PSNEXT and PSFEXT) and voltage transfer function (VTF) loss and crosstalk—used to evaluate the cumulative impact of multiple aggressor signals—as well as eye diagram and bit error rate (BER). Results show that CPI achieves twice the routing density of FS S1G1 while satisfying overall UCIe specifications, except VTF crosstalk at high-speed operation due to diagonal aggressors. Nevertheless, CPI outperforms FS SnG1 configurations, which fail to meet crosstalk specifications owing to insufficient shielding. To improve high-speed signal integrity of the CPI, two mitigation strategies are explored: widening the ground line and selectively converting diagonal signal lines into ground. These approaches effectively reduce crosstalk while maintaining CPI’s density advantage. The findings demonstrate that the CPI configuration is a promising interconnect structure for advanced packaging, offering both high throughput and design flexibility.