Bit-Accurate FPGA Current Control of a PV-STATCOM: Delay and Word-Length Limits for Ride-Through

The sampling-to-update delay and fixed-point word length that a PV-STATCOM current controller can tolerate during ride-through are rarely quantified against ride-through metrics, and complete fixed-point FPGA fast paths are rarely reported with post-route timing. A closed-loop dq-domain simulation reproduces an exact discrete-time model of the current loop to within 1.2e-6 pu. In a 640-case balanced-sag matrix no case fails at short-circuit ratio (SCR) 6 or higher with 0.5 pu or more retained voltage (192 of 192), while 120 of 128 cases fail at SCR 3 or lower with 0.2 pu or less. With fixed gains, current-step overshoot rises from 0 % to 82 % as the effective delay grows from 50 to 350 µs, and equal-margin retuning holds it near 5 % at the cost of DC-link margin in a stress sag. The loop is stable from 12 fractional bits and within ADC-level deviation from 18 to 20. A VHDL-2008 fast path in Q12.20 arithmetic (transforms, PLL, current controller, PWM, protection) matches its integer model without a mismatch in 400 profile ticks and 3 × 1500 random ticks. Vivado 2019.2 out-of-context implementation on an XC7Z020-1 meets 100 MHz (worst slack +0.219 ns) with 6480 LUTs, 6555 flip-flops and 65 DSP48E1; the control tick takes 208 clocks (2.08 µs @100 MHz ).