A 24Gb/s Switched-Capacitor Pre-Emphasis for PAM-3 Transmitters with Transition-Level Adaptation

In this study, a switched-capacitor peaking (SCP) feed-forward equalizer (FFE) is proposed to compensate for attenuation and distortion caused by channel loss in high-speed memory interfaces. The proposed SCP achieves both signal integrity enhancement and signal bandwidth preservation by implementing pre-emphasis while minimizing I/O capacitance (CIO). Furthermore, by pre-distorting according to the emphasis coefficient, the overhead of the output driver is minimized. The proposed SCP transmitter, implemented in a 28-nm CMOS process, compensates for −9.2 dB of channel loss at 8 GHz, achieving an energy efficiency of 0.129 pJ/b/dB with vertical and horizontal eye margins of 61 mV and 0.65 UI, respectively.

Authors

Publication Details

Journal
JSTS Journal of Semiconductor Technology and Science
Published
2026-10-22
DOI
https://doi.org/10.5573/jsts.2026.26.5.384
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
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article

A 24Gb/s Switched-Capacitor Pre-Emphasis for PAM-3 Transmitters with Transition-Level Adaptation

Jongchan An, Myeongju Park, Yoonsang Lee, Hyunsu Jang et al.
JSTS Journal of Semiconductor Technology and Science
Analog and Mixed-Signal Circuit Design
article

A 24Gb/s Switched-Capacitor Pre-Emphasis for PAM-3 Transmitters with Transition-Level Adaptation

Jongchan An, Myeongju Park, Yoonsang Lee, Hyunsu Jang, Junyoung Song
article en

Abstract

In this study, a switched-capacitor peaking (SCP) feed-forward equalizer (FFE) is proposed to compensate for attenuation and distortion caused by channel loss in high-speed memory interfaces. The proposed SCP achieves both signal integrity enhancement and signal bandwidth preservation by implementing pre-emphasis while minimizing I/O capacitance (CIO). Furthermore, by pre-distorting according to the emphasis coefficient, the overhead of the output driver is minimized. The proposed SCP transmitter, implemented in a 28-nm CMOS process, compensates for −9.2 dB of channel loss at 8 GHz, achieving an energy efficiency of 0.129 pJ/b/dB with vertical and horizontal eye margins of 61 mV and 0.65 UI, respectively.

JSTS Journal of Semiconductor Technology and ScienceVol. 26(5)
Openalex Percentile: Top 25%
Analog and Mixed-Signal Circuit Design
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