A Delay-Aware Verilog-A Modeling and Simulation Framework for Passive Photonic Integrated Circuits

Transmission delays are inherent in silicon photonic integrated circuits (PICs) and have a significant impact on their dynamic behavior and system-level performance. However, conventional modeling and simulation approaches often overlook or inadequately account for these delays, limiting accuracy and efficiency in circuit-level analysis. This paper presents a delay-aware macromodeling methodology that explicitly extracts time delays from frequency-domain responses and incorporates them into a compact pole-residue representation. In contrast to traditional techniques such as complex vector fitting (CVF), which approximate delay effects indirectly and often require a large number of poles, resulting in increased model complexity, reduced simulation efficiency, and potential causality violations, the proposed method captures delays explicitly and compactly without compromising accuracy or physical consistency. To enable integration into circuit simulation workflows, we introduce an efficient Verilog-A implementation of the proposed model, along with practical strategies for representing time delays within standard electronic-photonic co-simulation environments. The proposed approach is validated using three categories of passive PIC structures: waveguides, feedforward multi-path circuits, and resonant (loop-based) circuits, demonstrating superior compactness, simulation speed, and accuracy compared to conventional modeling techniques. These results highlight the method’s potential for scalable and high-fidelity modeling of PICs in hybrid electronic-photonic circuit and system design.