Employing Hybrid Image Processing for Grape Sorting

This contribution presents a practical realization of hybrid image processing for grape sorting. Hybrid image processing combines FPGA (Field Programmable Gate Array), GPU (Graphics Processing Unit), and CPU (Central Processing Unit) hardware with both rule-based and CNN (Convolutional Neural Network)-based algorithms to satisfy real-time constraints at high data throughput. A detailed end-to-end latency analysis of the complete sorting pipeline is provided. Our initial solution achieves a mean latency of 10.7 ms with a 99.9th percentile of 13.2 ms and a maximum latency of 14.0 ms. Our investigation reveals that the primary bottleneck lies in data handling rather than CNN inference. Furthermore, FPGA-based and CPU-based preprocessing approaches are compared using identical image data. A CPU-/GPU-based approach achieves a mean latency of 7.3 ms with a 99.9th percentile of 13.0 ms and a maximum latency of 13.5 ms. Finally, an improved FPGA architecture is proposed and evaluated, demonstrating improved timing performance. The improved FPGA solution achieves a mean latency of 9.0 ms with a 99.9% percentile of 10.6 ms and a maximum latency of 11.3 ms. The machine’s capability is evaluated at a grape processing throughput of 5.6 t/h.

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Publication Details

Journal
Sensors
Published
2026-10-16
DOI
https://doi.org/10.3390/s26206574
Primary Topic
Smart Agriculture and AI
Type
article
Field-Weighted Citation Impact
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article

Employing Hybrid Image Processing for Grape Sorting

Michael Heizmann, Simon Wezstein, Michael Stelzl
Sensors
Smart Agriculture and AI
article

Employing Hybrid Image Processing for Grape Sorting

Michael Heizmann, Simon Wezstein, Michael Stelzl
article en

Abstract

This contribution presents a practical realization of hybrid image processing for grape sorting. Hybrid image processing combines FPGA (Field Programmable Gate Array), GPU (Graphics Processing Unit), and CPU (Central Processing Unit) hardware with both rule-based and CNN (Convolutional Neural Network)-based algorithms to satisfy real-time constraints at high data throughput. A detailed end-to-end latency analysis of the complete sorting pipeline is provided. Our initial solution achieves a mean latency of 10.7 ms with a 99.9th percentile of 13.2 ms and a maximum latency of 14.0 ms. Our investigation reveals that the primary bottleneck lies in data handling rather than CNN inference. Furthermore, FPGA-based and CPU-based preprocessing approaches are compared using identical image data. A CPU-/GPU-based approach achieves a mean latency of 7.3 ms with a 99.9th percentile of 13.0 ms and a maximum latency of 13.5 ms. Finally, an improved FPGA architecture is proposed and evaluated, demonstrating improved timing performance. The improved FPGA solution achieves a mean latency of 9.0 ms with a 99.9% percentile of 10.6 ms and a maximum latency of 11.3 ms. The machine’s capability is evaluated at a grape processing throughput of 5.6 t/h.

SensorsVol. 26(20)
Karlsruhe Institute of Technology (DE)
Zero hunger, Industry, innovation and infrastructure
Openalex Percentile: Top 15%
Smart Agriculture and AI
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