Deterministic fixed point inference with tiled parallelism for ASIC implementation of human activity recognition

Abstract Deploying machine learning models on hardware platforms requires careful handling of numerical precision, limited resources, and predictable execution. In practice, mismatches between floating-point software models and their register-transfer level (RTL) implementations can lead to inconsistent inference results. In this proposed work, a hardware–software co-designed methodology that ensures bit-accurate and deterministic inference across floating-point and RTL implementations is proposed. A fully connected neural network with a 64–64–6 architecture is trained on the UCI human activity recognition (HAR) dataset and mapped to a hardware-friendly fixed-point representation. An application specific integrated circuit (ASIC)-oriented RTL design is developed and validated against a cycle-accurate Python fixed-point model to ensure consistency between software and hardware execution. To improve the performance, a tiled parallel multiply–accumulate (MAC) architecture with $$\textit{PAR}=8$$ is employed, enabling higher throughput without significantly increasing hardware complexity. The model achieves $$93.24\%$$ accuracy in floating-point and $$92.66\%$$ after fixed-point and RTL implementation, with a reduction of 0.58 percentage points following quantization. The RTL outputs match the fixed-point model across all evaluated samples, confirming its deterministic behavior. Synthesis using the TSMC 12 nm technology achieves a compute energy of 30.33 pJ per inference and a total inference energy of 170.67 pJ, demonstrating the suitability of the proposed methodology for edge AI applications.