Vertical Gate‐All‐Around SiGeSn/GeSn/SiGeSn Nanowire Transistors for Energy‐Efficient Electronics

ABSTRACT Conventional Si Complementary Metal Oxide Semiconductor (CMOS) technologies face increasing challenges in improving energy efficiency while maintaining device performance. Here, SiGeSn/GeSn heterostructures are employed as a unified Group‐IV platform for complementary vertical nanowire gate‐all‐around (GAA) MOSFETs and tunnel field‐effect transistors (TFETs) fabricated on Si wafers. The wider‐bandgap SiGeSn source/drain regions introduce band offsets to the GeSn channel, enabling heterostructure band engineering for leakage suppression and tunneling‐pathway control. Compared with all‐GeSn reference devices, the SiGeSn source/drain architecture suppresses drain‐induced barrier lowering and off‐state leakage without modifying the GeSn channel. The same heterostructure platform also enables complementary TFET operation, where the n‐TFET exhibits a subthreshold swing of 60 mV dec − 1 and a two‐order‐of‐magnitude enhancement in on/off current ratio. The performance difference between p‐ and n‐TFETs provides experimental evidence of the different efficiencies of indirect Γ‐to‐L and direct Γ‐to‐Γ tunneling processes. These results demonstrate that SiGeSn/GeSn heterostructures can be used to suppress leakage currents and engineer tunneling pathways, establishing SiGeSn/GeSn heterostructures as a unified Group‐IV platform for future energy‐efficient CMOS technologies beyond conventional Si.