High-performance recursive multiplier design using Motif-Based hierarchical elements and heterogeneous lyrebird attention networks

Digital Signal Processing (DSP), cryptography, and Machine Learning (ML) applications require multipliers that consume low power while delivering high speed and occupying minimal physical space, as computational demands continue to increase. Conventional multiplier architectures are limited due to high power consumption, increased delay, and large Power-Delay Product (PDP), which negatively impact overall system efficiency and energy utilization. This research proposes a highly Efficient Approximate Recursive Multiplier (EARM), designed to achieve a controlled trade-off between computational accuracy and hardware efficiency. The proposed method is based on the Motif Finite Hierarchical Element Heterogeneous Informed Graph Lyrebird Attention Network (MFHE-HIG-LAN), which is a combination of a Finite-Element-Informed Neural Network (FEI-NN) and a Motif-Based Hierarchical Heterogeneous Graph Attention Network (MBHAN). The model parameters are further optimized through the Lyrebird Optimization Algorithm (LOA) to discover the best approximation settings. Unlike exact multipliers, the proposed system is approximation-aware rather than fully exact, where controlled approximation is introduced in lower-significance computation blocks to reduce hardware complexity while maintaining acceptable output accuracy within predefined error bounds. The FEI-NN component learns physically informed error constraints, while MBHAN captures heterogeneous structural dependencies in multiplier sub-blocks through graph-based motif representations. LOA further optimizes the combined framework by selecting weight and configuration parameters that minimize a multi-objective fitness function involving power, delay, area, and error. To strengthen the connection between the AI framework and hardware optimization, the multiplier architecture is modeled as a heterogeneous graph where nodes represent arithmetic units (e.g., adders, compressors, and approximate multipliers) and edges represent signal dependencies across recursive stages. Training is performed using structured data derived from partial-product switching activity, critical-path delay, bit significance levels, and interconnect characteristics, enabling the model to learn approximation-sensitive regions effectively. Experimentally, the proposed design has resulted in considerable improvement in hardware efficiency compared to the previous methods, with the parameters Power = 64.32 µW, Area = 214.16 µm 2 , Delay = 0.396 ns, and PDP = 25.47 fJ, along with reduced error metrics compared to existing approaches. These results confirm that the proposed MFHE-HIG-LAN-based approximate recursive multiplier provides an effective balance between computational accuracy and hardware efficiency, making it suitable for energy-constrained applications.