DC‐to‐RF Optimization of a Charge‐Plasma Cylindrical Gate‐All‐Around Nanowire TFET Under Interface Trap Charge Variation

A detailed study of a charge plasma cylindrical gate‐all‐around (CP‐GAA) vertical nanowire (NW) tunnel field‐effect transistor (TFET) based on technology computer‐aided design (TCAD) is presented with effects of interface trap density ( D it ) on the device DC, analog, and RF characteristics. The device relies on an intrinsic silicon nanowire of 5 nm radius and 50 nm gate length and platinum and hafnium contacts to create hole‐ and electron‐rich charge‐plasma regions through work‐function engineering rather than conventional devices. The simulated results show that the positive interface trap charge can increase the electrostatic field and improve the source‐channel band alignment; thus, the band‐to‐band tunneling probability is increased. For D it = +1 × 10 13 cm −2 , the ON‐state current is 1.82 µA (compared to 1.20 µA for the neutral condition), and the average subthreshold swing improves from ~35 to 26 mV/dec. The same positive‐trap condition leads to a peak transconductance of about 165 µS/µm and a cut‐off frequency of about 600 GHz. The gate dielectric study shows that the ON current increases with increasing dielectric constant, giving the highest current of about 1.62 µA among the four dielectrics. All interface‐trap conditions show an average subthreshold swing lower than 40 mV/dec for the proposed TFET.