A low-voltage half-select free static memory with hybrid inverters for low-power and reliable WSN-based IoT architecture

Abstract The rapid development of wireless sensor network (WSN)-enabled Internet of Things (IoT) systems increases the necessity of designing SRAM cells with very low power dissipation, excellent stability, and reliable low-voltage operation. Nevertheless, traditional SRAM cells have problems of insufficient read/write stability, half select disturb, and higher susceptibility to process variations in nanometer technology nodes. In this paper, a CNTFET-enabled 10T SRAM cell with independent read/write paths, Schmitt trigger storage inverter, virtual ground write assistance, and half select disturb free operation is proposed to enhance the stability and energy efficiency. The new design is analysed in HSPICE by using the Stanford 32 nm CNTFET model and compared with the state-of-the-art CNTFET SRAM cells. Simulation results show that the proposed cell has 81% increase in read static noise margin (RSNM), 94% increase in write static noise margin (WSNM), 80% reduction in write power, 76% reduction in read power, 74% reduction in leakage power, 29% reduction in minimum operational voltage, and 109% increase in critical charge over the traditional 6T SRAM cell. Also, the RSNM and WSNM yields of the 1000 samples in Monte Carlo analysis are the largest, indicating immunity to process variations.