Unified Single-Transistor Cell for Multimode Reconfigurable Logic and Ternary In-Memory Search

Abstract The rapid growth of data-intensive applications demands efficient data processing with reduced data movement. Logic-in-memory (LIM) and in-memory search, exemplified by ternary content-addressable memory (TCAM), offer promising solutions; however, their typical implementation in separate device modules leads to increased circuit complexity and limited cell-level functional density. Here, we demonstrate a split-gate van der Waals ferroelectric field-effect transistor (vdW FeFET) as a unified operational cell for multimode reconfigurable logic and ternary in-memory search. The architecture integrates two parallel split gates, employing MoS2 as the channel and ferroelectric CuInP2S6 as the gate dielectric. Polarity-dependent modulation by the split gates and the drain bias enables multimode reconfigurable logic operation, supporting six Boolean functions, including directional data transfer. The same device can be programmed for associative memory equivalent to a one-transistor-per-cell TCAM, where two spatially separated ferroelectric regions are programmed within one continuous MoS2 channel, allowing ternary states to be stored and match and mismatch responses to be encoded directly into the channel current. Device-calibrated statistical simulations confirm ranking-based row discrimination under realistic device variability. By linking reconfigurable logic, spatial ferroelectric programming, and current-domain associative search within a common split-gate device framework, this work presents a compact transistor platform for logic-search-coupled in-memory computing.