Symmetry-Based Hybrid Winding Optimization Method for Reducing Position Error in a 12-4X Variable Reluctance Resolver

This paper proposes a computationally efficient winding optimization method for reducing the position error of variable reluctance resolvers. In practical resolver design, ideal signal-winding turns are generally noninteger and must be rounded for manufacturing, causing winding-turn errors that distort SIN/COS output voltages. In addition, harmonic components of air-gap permeance caused by leakage flux and magnetic saturation contribute to position error. To address these issues, an One-Shot FEA-based analytical model is developed to extract slot-wise permeance harmonics from a single transient FEA and predict position error for various winding configurations without repeated FEA. Furthermore, a symmetry-based winding quantization method is proposed for pole combinations satisfying p=2pw, where complementary floor and ceiling operations are applied to opposing slots to cancel winding-turn errors. The two methods are integrated into a hybrid winding optimization framework. For a 12–4X resolver, the proposed method reduces the average position error by approximately 64% compared with conventional rounding, while reducing computational time by approximately 99.78%. The method is further validated using an 18–6X resolver, demonstrating its applicability to other pole-slot combinations.