Chirality-Barrier skyrmion racetrack with topological protection, Hall effect suppression, and reconfigurable logic

Simultaneous suppression of the skyrmion Hall effect (SkHE) and preservation of skyrmion topological integrity remain critical challenges for skyrmion-based racetrack devices. We propose a chirality-engineered racetrack architecture in which a Dzyaloshinskii–Moriya interaction (DMI) sign reversal creates an energy barrier with a dual function: preserving skyrmion integrity by preventing inter-skyrmion merger into stripe domains, and providing a repulsive force that counterbalances the Magnus force to suppress the SkHE. The barrier also enables helicity-based encoding and reconfigurable AND/OR logic. By tuning the transition width w , the device operates in two regimes: crosstalk-free transport for w > 10 nm , and logic operations via inter-skyrmion interactions for w ≤ 10 nm . For w ≥ 20 nm , topological charge Q ≈ 2 is preserved throughout. Thiele-equation analysis identifies the off-diagonal SOT coupling integral I x y as the governing velocity parameter. An optimal width w = 20 nm maximizes the threshold current density ( J th = 2.7 × 1 0 12 A / m 2 ) and steady-state velocity ( v ̄ ∼ 296 m / s ). Barrier-force model verification confirms the analytic prediction F y = − 2 π R t F D 0 / w . This architecture provides a compact memory-logic integrated platform within a single racetrack.