Cu redistribution layers on permanent glass-core substrates for advanced packaging: Direct-on-glass and polymer build-up architectures

Glass-core substrates are attracting increasing interest for advanced packaging because of their dimensional stability, high electrical resistivity, smooth surfaces, and compatibility with fine-pitch interconnect processing. This review compares Cu redistribution-layer (RDL) technologies implemented on permanent glass-core substrates through two principal architectures: direct-on-glass RDLs and polymer build-up RDLs. Direct-on-glass approaches reduce dielectric-stack complexity and can support low-loss lateral routing, but their scalability depends strongly on glass–Cu adhesion, seed-layer control, conductor dimensional fidelity, and stress transferred to brittle glass. Polymer build-up approaches enable multilayer routing and microvia-based redistribution while introducing additional constraints associated with dielectric properties, cure-induced dimensional change, moisture response, interfacial integrity, and multilayer registration. Reported studies demonstrate micrometer-scale wiring and vias, broadband signal transmission, multilayer integration, accelerated reliability testing, and large-area glass processing. However, the most aggressive dimensions, highest integration levels, and strongest electrical or reliability results have generally been demonstrated in different material stacks and test vehicles rather than concurrently within a single permanent glass-core platform. Accordingly, minimum feature size alone should not be interpreted as a manufacturing design rule. Future progress will require coordinated design of interfaces, dielectric materials, metallization, and routing architecture, together with statistically meaningful qualification of dimensional control, electrical performance, environmental reliability, and panel-scale manufacturability.

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Publication Details

Journal
Materials Science in Semiconductor Processing
Published
2026-10-14
DOI
https://doi.org/10.1016/j.mssp.2026.111280
Primary Topic
3D IC and TSV technologies
Type
article
Field-Weighted Citation Impact
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article

Cu redistribution layers on permanent glass-core substrates for advanced packaging: Direct-on-glass and polymer build-up architectures

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Materials Science in Semiconductor Processing
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article

Cu redistribution layers on permanent glass-core substrates for advanced packaging: Direct-on-glass and polymer build-up architectures

Jaemyung Lim, Soobin Park, Hyun Jin Nam, Se-Hoon Park, Suin Chae, Da-Yeong Lee, Jinho Jo, Seonwoo Kim, Sang O. Kim, Jaemyeong Kang
article en

Abstract

Glass-core substrates are attracting increasing interest for advanced packaging because of their dimensional stability, high electrical resistivity, smooth surfaces, and compatibility with fine-pitch interconnect processing. This review compares Cu redistribution-layer (RDL) technologies implemented on permanent glass-core substrates through two principal architectures: direct-on-glass RDLs and polymer build-up RDLs. Direct-on-glass approaches reduce dielectric-stack complexity and can support low-loss lateral routing, but their scalability depends strongly on glass–Cu adhesion, seed-layer control, conductor dimensional fidelity, and stress transferred to brittle glass. Polymer build-up approaches enable multilayer routing and microvia-based redistribution while introducing additional constraints associated with dielectric properties, cure-induced dimensional change, moisture response, interfacial integrity, and multilayer registration. Reported studies demonstrate micrometer-scale wiring and vias, broadband signal transmission, multilayer integration, accelerated reliability testing, and large-area glass processing. However, the most aggressive dimensions, highest integration levels, and strongest electrical or reliability results have generally been demonstrated in different material stacks and test vehicles rather than concurrently within a single permanent glass-core platform. Accordingly, minimum feature size alone should not be interpreted as a manufacturing design rule. Future progress will require coordinated design of interfaces, dielectric materials, metallization, and routing architecture, together with statistically meaningful qualification of dimensional control, electrical performance, environmental reliability, and panel-scale manufacturability.

Materials Science in Semiconductor ProcessingVol. 218
Korea Electronics Technology Institute (KR), Anyang University (KR)
Industry, innovation and infrastructure
Openalex Percentile: Top 24%
3D IC and TSV technologies
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